1. Field of the Invention
The present invention relates to a semiconductor storage device, and specifically to a semiconductor storage device having an input data hold circuit which operates in synchronization with a rising edge of a system clock signal.
2. Description of the Related Art
In recent years, along with the increase in operation speed of microprocessors, etc., demand for semiconductor storage devices which operate at higher speed has been growing. A semiconductor storage device developed for the purpose of meeting such a demand is a synchronous semiconductor storage device that operates in a synchronous burst operation mode. In such a storage device, high speed readout of data is achieved in addition to the increase in speed for normal random access, although an access method is limited to some extent.
The synchronous burst operation mode used in a clock synchronous semiconductor storage device is a high speed access mode in which predetermined data rows are sequentially output in synchronization with a system clock signal.
One example of a synchronous semiconductor storage device which operates in a synchronous burst operation mode includes a synchronous DRAM (hereinafter, referred to as xe2x80x9cSDRAMxe2x80x9d). In an SDRAM, upon receiving the system clock signal, an input circuit receives, in synchronization with a rising edge of the pulse of the system clock signal, control signals (a row address strobe signal, a column address strobe signal, a write enable signal, and a chip select signal) and an address signal from outside in a time-division manner.
When the control signals and the address signal are received in synchronization with a rising edge of a system clock signal, it is necessary that the control signals and the address signal are input with consideration for a certain setup time and a certain hold time with respect to the rising edge of the system clock signal. In high speed devices such as SDRAMs developed in the recent years, as the frequency of the system clock signal increases, the setup time and the hold time are reduced. Thus, in the margin settings of the setup time and the hold time based on the specification of a storage device, a reduction in dead time is demanded more than ever.
For the purpose of meeting such a demand, a structure of a flip-flop for latching a data signal, which compensates for the setup time, has been proposed. In general, it is necessary to delay an internal clock signal when an input data signal and a system clock signal are input so that waveforms of these two signals rise up at almost the same timing. However, such a delay of the internal clock signal delays the output of data. In the proposed structure, the difference between a delay of the control signals and the address signal in an input data latch circuit section and a delay of a rising edge of the system clock signal is eliminated, whereby the setup time is compensated.
FIG. 8 shows a latch circuit 800 disclosed in Japanese Laid-Open Publication No. 2-203611. In the latch circuit 800, a chip select signal CS, and an address signal (A0-Ax) are input to a logic circuit 204 through a CS input buffer 202 and an address buffer 203, respectively. The logic circuit 204 outputs a signal xcfx86204 to a latch circuit 20. The latch circuit 20 includes a transfer gate 21a, a transfer gate 22a, an inverter INV21, an inverter INV22, an inverter INV23, an inverter INV24, and an inverter INV25. The transfer gate 21a includes an NMOS transistor N21 and a PMOS transistor P21. The transfer gate 22a includes an NMOS transistor N22 and a PMOS transistor P22.
Upon receiving a clock signal CLK, a CLK input buffer 205 outputs a CLK input buffer output signal xcfx86205. A delay circuit 201 receives the CLK input buffer output signal xcfx86205 and outputs a signal xcfx86201 to the transfer gate 21a and the transfer gate 22a. Specifically, the signal xcfx86201 is input directly to a gate of the PMOS transistor P21 and a gate of the NMOS transistor N22, and input through the inverter INV25 to a gate of the NMOS transistor N21 and a gate of the PMOS transistor P22.
The signal xcfx86204 from the logic circuit 204 is supplied to the transfer gate 21a of the latch circuit 20. A signal output from the transfer gate 21a is supplied to the inverter INV21. A signal output from the inverter INV21 is supplied to the transfer gate 22a and is also fed back to the inverter INV21 through the inverter INV22. An output of the transfer gate 22a is output from the latch circuit 20 through a feedback loop formed by the inverter INV23 and the inverter INV24, and supplied to a transfer gate 23a. 
The signal output from the delay circuit 201 is also supplied through an inverter INV26 to one of input terminals of a NAND gate NAND21. The other input terminal of the NAND gate NAND21 receives the CLK input buffer output signal xcfx86205 from the CLK input buffer 205. An output of the NAND gate NAND21 is supplied to gates of the transfer gate 23a and gates of a transfer gate 24a. The transfer gate 23a includes an NMOS transistor N23 and a PMOS transistor P23. The transfer gate 24a includes an NMOS transistor N24 and a PMOS transistor P24. The output of the NAND gate NAND21 is supplied directly to a gate of the NMOS transistor N23 and a gate of the PMOS transistor P24, and is also supplied through the inverter INV27 to a gate of the PMOS transistor P23 and a gate of the NMOS transistor N24. The signal xcfx86204 from the logic circuit 204 is also supplied to the transfer gate 24a. A buffer Buf21 receives an output of the transfer gate 23a and an output of the transfer gate 24a, and outputs a signal xcfx8621.
In the latch circuit 800 having the above structure, an internal clock signal is delayed so as to obtain a margin for a setup time, whereby the delay of the input data signal (A0-Ax) with respect to the internal clock signal is eliminated.
Specifically, in the latch circuit 20 whose setup time determined based on the specification of the latch circuit 20 is 0, the input data signal (A0-Ax) and the system clock signal CLK arrive at the latch circuit 20 at the same time. Utilizing this, the system clock signal is delayed by the delay circuit 201 to generate an internal clock signal. Until the input data signal (A0-Ax) is latched based on the internal clock signal, the already-arrived input data signal (A0-Ax) is routed through a path different from the latch circuit 20, i.e., through the transfer gate 23a and the transfer gate 24a (which have been turned on), and are output from the buffer Buf21.
According to this system, the address data signals are input under the timing control of data input control command signals (RAS, CAS, WE, and CS). Therefore, it is required to hold the address data signal when the data input control command signals are input, in order to obtain an input data signal for internal access. For the purpose of solving such a problem, an input data hold circuit 900 (FIG. 9) further including a latch circuit 51 for holding signals has been proposed.
In the input data hold circuit 900, a signal xcfx8652 generated by a latch circuit 53 having the same structure as that of the latch circuit 800 as shown in FIG. 8 is supplied to a latch circuit 51. The latch circuit 51 includes a transfer gate 55a, a transfer gate 56a, an inverter INV59, an inverter INV510, an inverter INV511, an inverter INV512, an inverter INV513. The transfer gate 55a includes an NMOS transistor N55 and a PMOS transistor P55. The transfer gate 56a includes an NMOS transistor N56 and a PMOS transistor P56.
The signal xcfx8652 generated by the latch circuit 53 is supplied to the transfer gate 55a. An input data control signal xcfx86120 is supplied to a gate of the PMOS transistor P55 and a gate of the NMOS transistor N56. Furthermore, the input data control signal xcfx86120 is also supplied to a gate of the NMOS transistor N55 and a gate of the PMOS transistor P56 through the inverter INV513.
An output of the transfer gate 55a is supplied to the inverter INV59. An output of the inverter INV59 is supplied to the transfer gate 56a and is also fed back to the inverter INV59 through the inverter INV510. An output of the transfer gate 56a is supplied to a feedback loop formed by the inverter INV511 and the inverter INV512, and then, the latch circuit 51 outputs signals Ain0-Ainx from the inverter INV511.
The input data hold circuit 900 having the above structure is relatively large in size. Furthermore, since the internal clock signal used for latching in the latch circuit 50 is delayed by the delay circuit 501, the internal access time is delayed accordingly for the same length of time.
In addition to such problems, in the input data hold circuit 900, it is required to provide an input data control signal generation circuit 1000 (see FIG. 10) for generating the input data control signal xcfx86120 in order to hold an input data address signal when the data input control command signal is input. FIG. 11 shows a timing chart of the input data hold circuit 900. As seen from FIG. 11, the internal access time is the sum of the delay time caused by the input data control signal generation circuit 120 (FIG. 10) and input buffers associated therewith, the delay time caused by the logic circuit 504 and input buffers associated therewith, and the delay time caused by the latch circuit 51.
Japanese Laid-Open Publication No. 8-17182 discloses a structure which shortens the internal access time. In this structure, when the setup time based on the specification is several nanoseconds, a part of the setup time is allocated to the internal access time, whereby the internal access time is shortened.
FIG. 12 shows a logic data input latch circuit 1200 disclosed in Japanese Laid-Open Publication No. 8-17182. In the logic data input latch circuit 1200, a chip select signal CS and address signal (A0-Ax) are supplied to logic circuit 74 through a CS input buffer 72 and an address buffer 73, respectively. The logic circuit 74 output a signal xcfx8674 to a latch (flip-flop) circuit 70. The latch (flip-flop) circuit 70 includes a transfer gate 71a, a transfer gate 72a, an inverter INV71, an inverter INV72, an inverter INV73, an inverter INV74, and an inverter INV75. The transfer gate 71a includes an NMOS transistor N71 and a PMOS transistor P71. The transfer gate 72a includes an NMOS transistor N72 and a PMOS transistor P72. The latch (flip-flop) circuit 70 receives the signal xcfx8674 from the logic circuit 74 at the transfer gate 71a. A CLK input buffer 71 receives a system clock signal CLK and outputs a CLK input buffer output signal xcfx8671 to a gate of PMOS transistor P71 and a gate of NMOS transistor N72. The CLK input buffer output signal xcfx8671 is also supplied to a gate of the NMOS transistor N71 and a gate of the PMOS transistor P72 through the inverter INV75. An output of the transfer gate 71a is supplied to the inverter INV71. An output of the inverter INV71 is supplied to the transfer gate 72a and is also fed back to the inverter INV71 through the inverter INV72. An output of the transfer gate 72a is supplied to a feedback loop formed by the inverter INV73 and the inverter INV74, and then, an output of the inverter INV73 is output as a signal xcfx8675.
In the logic data input latch circuit 1200, the logic circuit 74, which receives the input (address) data signals through the address buffer 73, and an interconnection associated therewith are positioned before the latch (flip-flop) circuit 70. In such a structure, the delay time caused by the logic circuit 74 and the interconnection associated therewith is interleaved with the setup time, and the time consumed from a rising edge of the system clock signal CLK to the exit of an output signal xcfx8675 from the latch circuit 70 is shortened.
In the logic data input latch circuit 1200, the delay time caused to the data address signal (A0-Ax) in the path from the address buffer 73 to the latch (flip-flop) circuit 70 is longer than the delay time caused to the system clock signal CLK in the path from the CLK input buffer 71 to the latch (flip-flop) circuit 70 by the delay time caused by the logic circuit 74 and the interconnection associated therewith. In such a case, if the system clock signal CLK and the data address signal (A0-Ax) are input at the same time (i.e., if the signal xcfx8671 and the signal xcfx8673 are output at the same time from the CLK input buffer 71 and the address buffer 73, respectively), in view of the timing of latching the data address signal (A0-Ax) by the latch (flip-flop) circuit 70, the delay time caused by the logic circuit 74 and the interconnection associated therewith reduces the margin of the setup time.
Thus, in the above circuit structure, the delay time caused by the logic circuit 74 and the interconnection associated therewith should be shorter than the setup time.
Furthermore, in a synchronous semiconductor storage devise such as an SDRAM, address data signals are generally input under the timing control of data input control command signals. Therefore, in addition to securing sufficient margins for the setup time and the hold time by the latch (flip-flop) circuit 70, the address data signals input in synchronization with a rising edge of the system clock signal must be held when the data input control command signals are input. Thus, it is necessary to provide, subsequent to the latch (flip-flop) circuit 70, a flip-flop circuit for holding the address data signal (for example, a flip-flop circuit 802 shown in FIG. 13).
An input data hold circuit 1300 as shown in FIG. 13 has a two-stage flip-flop circuit 80 including flip-flop circuits 801 and 802. Such a two-stage structure enables the input data hold circuit 1300 to hold the address data signal. The structure of the flip-flop circuit 802 additionally provided for holding the address data signal is the same as that of the latch circuit 51 shown in FIG. 9.
FIG. 14 shows a timing chart for the input data hold circuit 1300. As seen from this chart, the internal access time is the sum of the delay time caused by the logic circuit 84 and input buffers associated therewith, the delay time caused by the input data control signal generation circuit 120 (FIG. 10) and input buffers associated therewith, and the delay time caused by the latch circuit 802.
In the flip-flop circuit 80 shown above, the address data signal latched by the flip-flop circuit 801 at a rising edge of the system clock signal is held based on the input data control signal xcfx86120 generated by the input data control signal generation circuit 1000 (see FIG. 10) which receives the system clock signal CLK and the data input control command signals. Then, the address data signal is supplied to an internal circuit (a memory section of the storage device) through the inverter INV88.
In such a case, the input data control signal xcfx86120 includes the delay time caused by the input data control signal generation circuit 1000 with respect to a rising edge of the system clock signal. However, since sufficient margins of the setup time and the hold time are secured by the flip-flop circuit 801, the address data signal input in synchronization with a rising edge of the system clock signal is held until the subsequent rising edge of the system clock signal. Thus, the address data signal including a margin of about one cycle of the system clock signal can be held by the flip-flop circuit 802.
However, the flip-flop circuit 80 is relatively large in size because it includes two flip-flop circuits. Furthermore, this flip-flop circuit is provided for each address data signal. Thus, this circuit occupies a relatively large area on a semiconductor chip.
The flip-flop circuit 80 shown in FIG. 13 requires two flip-flop circuits (801 and 802) because the system clock signal CLK is used to latch an input data signal. In the case where the system clock signal CLK is replaced with a clock signal having a single pulse (which has been generated from an externally provided clock input signal having a series of pulses in response to the data input control command input signal) to latch an input data signal, the input data signal can be latched and held by a single flip-flop circuit 901 as shown in FIG. 15. In FIG. 15, in place of the clock signal CLK externally supplied through the CLK input buffer 71 to the logic data input latch circuit 1200 (FIG. 12), the input data control signal xcfx86120 is supplied to a flip-flop circuit 901.
However, in FIG. 15, it is necessary to provide a logic circuit 126 (FIG. 10) for generating a clock signal of a single pulse from an externally supplied clock signal having a series of pulses. The generated clock signal having a single pulse includes a delay time caused by the logic circuit 126. That is, the increase in internal access speed, which is a feature of the circuit disclosed in Japanese Laid-Open Publication No. 8-17182, cannot be achieved. Moreover, in the case where the delay time caused by the logic circuit 126 for generating a clock signal having a single pulse is longer than the delay time caused by the logic circuit 94 (FIG. 15) which is subsequent to the initial stage to which data input addresses are supplied, a margin of the hold time is reduced.
In a clock synchronous semiconductor device, an input data signal is input in synchronization with a rising edge of a clock signal. Therefore, a sufficient setup time and hold time must be secured for inputting the input data signal. However, in the input data hold circuit 1300 (FIG. 13), the number of logic circuit stages is different between a path for the clock signal from its input terminal to a latch circuit and a path for the input data signal from its input terminal to the latch circuit, and this difference in the number of stages causes a skew between these signals. This skew reduces a margin of the setup time and the hold time. Therefore, it is desirable that the number of logic circuit stages is the same between the paths to the latch circuit for the clock signal and for the input data signal. However, in the input data hold circuit 1300, the number of logic circuit stages is larger in the path for the input data signal than in the path for the system clock signal, and thus, a margin of the setup time is reduced.
Alternatively, in the input data hold circuit 900 (FIG. 9), a skew between a clock signal and an input data signal can be eliminated by inserting a logic in a path for the clock signal to a latch circuit so that the number of logic circuits in the path for the clock signal to the latch circuit is the same as those in the path for the input data signal to the latch circuit. However, in such a structure, although a margin can be secured for the setup time and the hold time, the insertion of the logic circuits for the purpose of eliminating the skew increases a dead time, and accordingly, the internal access time is increased.
According to one aspect of the present invention, a synchronous semiconductor storage device which operates in synchronization with a system clock signal includes: a first feedback loop which latches an address data signal; a first latch circuit including a first transfer gate which controls the latching by the first feedback loop of the address data signal; a second feedback loop which holds the address data signal latched by the first feedback loop; a second latch circuit including a second transfer gate which controls the holding by the second feedback loop of the address data signal latched by the first feedback loop; a data input control signal generation circuit for generating a data input control signal based on the system clock signal and control signals; and an address latch signal generation circuit for generating an address latch signal from a logical sum of the system clock signal and the data input control signal, wherein the address latch signal is input to the first transfer gate to control the latching of the address data signal, and the data input control signal is input to the second transfer gate to control the holding of the address data signal latched by the first feedback loop.
In one embodiment of the present invention, the control signals include a row address strobe signal, a column address strobe signal, a write enable signal, and a chip select signal.
In another embodiment of the present invention, the synchronous semiconductor storage device further includes a logic circuit for generating a data signal to be latched by the first latch circuit based on the chip select signal and the input address signal.
In still another embodiment of the present invention, a delay time caused by the address latch signal generation circuit is equal to a delay time caused by the logic circuit.
In still another embodiment of the present invention, a falling edge of the data input control signal is within a low period of the system clock signal in the same cycle.
In still another embodiment of the present invention, the synchronous semiconductor storage device includes a plurality of first latch circuits and a plurality of second latch circuits so as to latch a plurality of address data signals at the same time.
In still another embodiment of the present invention, the data input control signal generation circuit and the address latch signal generation circuit each have a function of a buffer.
According to the present invention having the above structure, a logic circuit and interconnections which are required before a latch circuit that latches an input data signals are provided in paths to the latch circuit for a system clock signal and a input data signal so that the delay time caused to the system clock signal is the same as that caused to the input address signal, whereby a skew between the system clock signal and the input address signal does not occur. As a result, sufficient margins can be secured for a setup time and a hold time when the input data signal is latched. In addition, the input data signal latched after it has been delayed by a data input control signal generation circuit can be held, and therefore, the internal access speed is relatively high.
Furthermore, a circuit having the above features can be formed relatively small in size. Therefore, the circuit does not increase the size of an entire device as compared to the conventional structure.
Thus, the invention described herein makes possible the advantage of providing an input data latch circuit in which a sufficient setup time and hold time with respect to the system clock signal are secured, and at the same time, the internal access speed is increased without increasing the size of an entire device.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.